1. Field of the Invention
This invention relates to a semiconductor integrated circuit having a scan test function that facilitates testing of the semiconductor integrated circuit.
2. Description of the Related Art
In general, a large scale integrated circuit (hereafter referred to as an LSI) undergoes a GO/NO-GO test by an LSI tester before shipping. It is necessary that a test pattern used in the GO/NO-GO test is designed to be capable of detecting failures in a plurality of logic circuits constituting the LSI as thoroughly as possible.
However, testing all the logic circuits requires an enormous amount of test vectors and test time as the scale of the LSI becomes large. In order to solve the problem, so-called Design for Testability has been put into practice.
The Design for Testability is a design technology that a test plan of an LSI is taken into consideration in a design stage of the LSI and test circuits are embedded in the LSI. Observability and controllability are basic concepts that indicate testability of the LSI. A circuit with good observability means that a logical value at a certain node in the circuit can be easily measured from outside, while a circuit with good controllability means that a logical value at a certain node in the circuit can be easily set by inputting data from outside. The better the observability and the controllability are, the more easily an effective test pattern can be created. As a result, a failure detection rate of the logic circuits constituting the LSI is improved. A scan test circuit is one of the test circuits that enhance the observability and the controllability.
The scan test circuit includes a plurality of flip-flops, each of which is disposed corresponding to each of logic circuits in the LSI. The plurality of flip-flops form a shift register when connected in a chain formation. The scan test circuit performs a shift operation that is sequentially shifting data taken into the flip-flops and capture operation that is capturing an output of each of the logic circuits into corresponding each of the flip-flops.
That is, data in each of the flip-flops is provided to each of the logic circuits as a test signal by a first shift operation. Next, output data of each of the logic circuits is taken into each of the flip-flops by the capture operation. Then, the output data of each of the logic circuits taken into each of the flip-flops is sequentially outputted from the flip-flop in the last stage by the shift operation that follows. A GO/NO-GO judgment on each of the logic circuits is made by comparing the output data of each of the logic circuits with its expected value. Technologies related to the scan test circuit are disclosed in Japanese Patent Application Publication No. 2001-59856, for example.
The scan test circuit described above is also embedded in a semiconductor integrated circuit that incorporates both digital circuits and analog circuits. In most cases, a maximum operating frequency of the shift register during the scan test is higher than a maximum allowable operating frequency of the analog circuits. Therefore, if a high frequency output signal of the flip-flop is transferred to the analog circuit during the scan test, there is a risk that the analog circuit is destroyed because the high frequency output signal of the flip-flop exceeds the maximum allowable operating frequency of the analog circuit.